A Novel Autocorrelation Combined MM-CDR Time-Interleaved ADC Timing Calibration in 28 nm CMOS Technology

Abstract

With the great improvement in data transmission rate requirements, the analog-to-digital converter (ADC)-based wireline receiver has received more attention due to its flexible and powerful equalization capability. Time-interleaved ADC (TI-ADC) is the most commonly used architecture in high-speed ADC-based receivers. One of the major challenges in TI-ADC is the timing mismatch between the parallel sub-ADCs. The traditional skew detection and calibration circuits consume substantial power and area of the receiver system. In this article, we propose a novel calibration method using the autocorrelation principle combined with an existing Mueller–Müller clock and data recovery circuit (MM-CDR). This new method reuses the existing error-direction information of the MM-CDR in the ADC-based wireline receiver and combines the autocorrelation principle to obtain the timing mismatch information in the TI-ADC without adding an additional skew deviation extraction circuit, which greatly reduces the area and power consumption. In order to demonstrate the effectiveness and superiority of our skew calibration method, we designed a complete ADC-based wireline receiver circuit using the 28 nm CMOS technology. The simulation results show that our proposed calibration method could obtain 0.193 sensitivity per 1% skew, which was superior to traditional calibration methods. To verify the speed and accuracy of the convergence of our calibration method, the initial skews were set to +0.4 ps, +0.2 ps, −0.59 ps, and 0 ps for our 4 × 8 TI-ADC; the spurious free dynamic range (SFDR) and signal-to-noise and distortion ratio (SNDR) of the ADC were increased from 37.24 dB and 31.28 dB to 48.07 dB and 34.56 dB, respectively, after timing calibration with a 50 fs step. In order to compare the area and power consumption required by different skew calibration methods, we synthesized the expressions of various methods using the 28 nm CMOS technology, and the area and power consumption of our proposed skew calibration loop were 695 μm2 and 0.126 mW, respectively, which were the smallest among these methods.