A novel approach to mitigate stress induced defects at metal-dielectric interface in Redistribution layers for 3D IC stacking

Abstract

Abstract The reliability of a redistribution layers in 3D IC is dependent on how well the different shape and size of metal connection with varying density are connected at the different metallization levels. The widely different coefficient of thermal expansion of metal (Cu ~16.5 × 10−6 m/mK) and dielectric (SiO2 ~ 3 × 10−6 m/mK) often leads to defects, such as cracking at the metal-dielectric interface. In this work, we present a manufacturing level friendly process modification to the conventional approach to present an almost crack free metal-dielectric interface for subsequent processing in the RDL fabrication. After the copper electroplating and chemical mechanical planarization (CMP), we use a cap layer to protect the top layer and anneal the metal. Finally, we repeat the CMP to remove the cap layer before sending the wafers for subsequent processing.