A new ViT-Based augmentation framework for wafer map defect classification to enhance the resilience of semiconductor supply chains

Abstract

Wafer map defect classification plays a crucial role in sustaining the semiconductor supply chain during industrial disruptions by ensuring continuity, resilience, and efficiency while aligning with sustainability principles. Up to 30 percent of production costs is lost to chip testing and yield losses for semiconductor manufacturing supply chain. In the semiconductor practice, wafer map defects recognition plays a linchpin role in the front-end-of-line stage. Defect pattern recognition can directly pinpoint the assignable causes and provide the domain experts with actionable insights. However, various wafer defect types occur differently from each other, which makes the collected wafer map dataset to be highly imbalanced in defect classes. In the face of data imbalance, the classification model usually cannot provide satisfactory classification performance. In this aspect, this paper intends to investigate the wafer defect map classification problem by using Vision Transformer (ViT) as an alternative data augmentation approach. The primary purpose is to alleviate the class-imbalance issue and then the performance of a deep learning-based convolutional neural network for wafer defect classification can be effectively improved. The experimental results demonstrate that the proposed data augmentation method by using ViT proves to be a potential generative model for improving wafer map defect classification, particularly robust on the individual minority class. In a word, the proposed augmentation framework for wafer map defect classification facilitates a more targeted and efficient approach to quality control, resource utilization, and production optimization in maintaining a sustainable semiconductor supply chain, particularly in times of industrial disruption.