Abstract
In this paper a 0.9V high gain, high speed two-stage Op-Amp is designed and simulated in a 0.18µm CMOS technology. Using both bulk-driven and positive feedback techniques, the dc gain of this Op-Amp is increased about 18.5dB without consuming more power. In addition, the frequency response of the proposed Op-Amp is investigated. Compared to the conventional Op-Amp structure, it is shown that in the proposed Op-Amp, in spite of the decrease of the first pole, the other poles and zeros are not changed. In other words, while the UGBW and phase margin are identical for both conventional and proposed Op-Amps, in the proposed Op-Amp, the pole splitting is performed better than its conventional counterpart. The simulation results show a dc gain of 94dB, unity gain frequency of 549MHz and phase margin of 68°. The slew rate is 200V/µs and the Op-Amp dissipates about 2.73mW from a 0.9V supply voltage.
Published Version
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