A new true-single-phase-clocked double-edge-triggered flip-flop for low-power VLSI designs

Abstract

A new CMOS double-edge-triggered flip-flop (DETFF) utilizing true single phase clocking is proposed as a promising storage element in low-power VLSI designs. Compared to the previously reported DETFF's, both the total transistor count and the number of clocked transistors per flip-flop are reduced to save the power consumption. A clock system is defined in this paper to include a clock generator, clock distribution networks, and clocked flip-flops. Different amounts of power consumption of the different clocking system with different edge-triggered flip-flops are analyzed and compared. It is found that this newly proposed DETFF requires less power in every respect. For example, using the proposed DETFF can save up to 36% of power consumption in the clocking system for a pipelined FIR macro.