A new transition count method for testing of logic circuits

Abstract

The authors propose a transition count method for detecting faults in single- and multiple-output logic circuits. It can be extended to sequential circuits in which scan design is incorporated. This method is called double transition count (DTC) testing for single-output circuits and multiple transition count (MTC) testing for multiple-output circuits. It is shown that the detectability of faults obtained by DTC and MTC testing is the same as that obtained by conventional testing. Hence, this method does not result in any information loss even though the set of output vectors is considerably compressed. The size of a DTC or MTC test is equal to the size of the equivalent conventional test since no test vectors need to be repeated. The basic test circuitry required is very simple, consisting of only one flip flop, one OR gate, one inverter, and one switch per output.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>