Transition Count Testing of Combinational Logic Circuits

Abstract

Logic circuits are usually tested by applying a sequence of input patterns S to the circuit under test and comparing the observed response sequence R bit by bit to the expected response Ro. The transition count (TC) of R, denoted c(R), is the number of times the signals forming R change value. In TC testing c(R) is recorded rather than R. A fault is detected if the observed TC c(R) differs from the correct TC c(Ro). This paper presents a formal analysis of TC testing. It is shown that the degree of detectability and distinguishability of faults obtainable by TC testing is less than that obtainable by conventional testing. t is argued that the TC tests should be constructed to maximize or minimize c(Ro). General methods are presented for constructing complete TC tests to detect both single and multiple stuck-line faults in combinational circuits. Optimal or near-optimal test sequences are derived for one-and two-level circuits. The use of TC testing for fault location is examined, and it is concluded that TC tests are relatively inefficient for this purpose.