A new technique to measure the thermal resistance of LDMOS transistors

Abstract

This paper introduces a new dc technique for the extraction of the thermal resistance of LDMOS transistors. The new extraction method has distinctive advantages over existing techniques: 1) it is based on dc measurements of the I-V output curves at different ambient temperatures, thus requiring only very standard and inexpensive equipment, with the exception of a stable and accurate temperature control; 2) it does not need any special layout or test structure, nor any knowledge of the physical structure of the device under test; and 3) it can be applied to both packaged and on-wafer FETs. We applied the new technique to LDMOS transistors with a wide range of gate widths, namely, 2.68-84.42 mm, obtaining well-behaved and consistent results. A comparison of the new method with a standard extraction technique based on short-pulse measurements at different ambient temperatures showed substantial agreement between the two.