S-parameter measurement prediction for bipolar transistors using a physical device simulator

Abstract

S-parameter data characterizing bipolar IC test structures (including layout parasitics) are derived from two-dimensional device simulations of a submicrometer emitter bipolar transistor (BJT). The modeling used for the calculation of the BJT test structure S-parameter response is reported. The effects of interconnect and bond pads used in the IC test structure layout are evaluated. In addition, a two-layer metal interconnect-based test structure with very low signal loss is proposed. This result has applications in: (1) designing BJT test structures for IC technologies, (2) supplementing existing two-port S-parameter measurements to provide three-port characterization, and (3) evaluating the accuracy of on-chip S-parameter calibration techniques for specific IC test structure layouts. >