A new recursive shared segmented split multiply-accumulate unit for high speed digital signal processing applications

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A new recursive shared segmented split multiply-accumulate (MAC) unit have been proposed which can be deployed in high speed DSP applications like Fast Fourier Transform (FFT), Discrete Cosine Transform (DCT), Wavelet Transform (WT) and digital filtering. This paper presents two design aspects, the former presents the design of new parallel prefix adder which is responsible in the generation of partial product addition in PPRT network. The latter explains the design of recursive shared segmented split MAC. The performance of the proposed parallel prefix adder and MAC unit are tested in terms of ASIC and FPGA. In FPGA the MAC structure is coded using Verilog HDL using the targeted device Virtex6 Lower power XC6VLX75TL. The performance of MAC in FPGA is examined in terms of slice-LUT utilization, logical level, combinational and sequential path delay, power and ST (product of slice utilization and combinational/sequential delay). In ASIC the HDL code of MAC block is synthesized using the TSMC 180nm technology. The performance of MAC is analyzed in terms of delay, power, PDP, gate count, Figure of Merit (FOM) and throughput with its counterpart.