Abstract
In today's smart and fast computing world, the designing of high speed and low energy consumption based Digital Signal Processors (DSPs) is a realistic and ever embryonic area of research. Conversely, the design of a proficient Digital Signal Processor intended to carry out the complex computations associated with image processing or signal processing involves the design of an efficient Multiply-Accumulate (MAC) unit which is one of the most vital blocks of processor. The multiplier, adder, accumulator are the fundamental construction sub-units for MAC units. Moreover, the computation carried out with the extensive and appropriate usage of Vedic Mathematics is set up to be well proficient and capable as compared to the basic Mathematics. This paper has presented the implementation of novel 32-bit MAC unit consisting of Vedic Multiplier using Urdhva Tiryakbhyam sutra and efficient adder circuit using Modified Weinberger adder technique. From comparative analysis, the MAC unit designed was found to be proficient in terms of delay and energy consumed.
Published Version
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