Abstract
A monolithic multi-hit digital TDC (time-to-digital converter) has been developed for the DUMAND II experiment. This TDC has a 27 channel pipelined architecture, with a 1ns least count. An overview of the performance requirements and implementation in a GaAs gate array is described here.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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