A high density GaAs gate array architecture

Abstract

A GaAs gate array family has been developed incorporating from 100000 to 350000 raw two-input NOR gates in a sea-of-gates architecture. These arrays exhibit unloaded gate delays of 50 ps and a worst-case power dissipation of 250 mu W. The authors describe the gate array cells and I/O buffers that were designed with a 0.6- mu m L/sub eff/ self-aligned gate GaAs MESFET process. In addition, the array architecture is described along with the test results on a 100 K gate array test chip designed to verify array performance. >