Abstract
A new method for implementing two-level logic circuits, which exhibit minimal power dissipation, is introduced. Switching activity reduction of the logic network nodes is achieved by adding extra input signals to specific gates. Employing the statistic properties of the primary inputs, a new concept for grouping the input variables with similar features is introduced. Appropriate input variables are chosen for reducing the switching activity of a logic circuit. For that purpose, an efficient synthesis algorithm, which generates the set of all groups of the variables and solves the minimum covering problem for each group is developed. The comparison of the results, produced by the proposed method, and those from ESPRESSO shows that a substantial power reduction can be achieved.
Highlights
The modern design techniques require to take into consideration in addition to the two traditional design parameters, area and speed, a third one, power dissipation [1,2, 3]
The Transition function depends on the primary inputs and takes the logic value one if and only if a transition occurs between two successive clock cycles
The proposed method for minimizing power dissipation of a function F is implemented by a new synthesis tool, which can be considered as a modified ESPRESSO
Summary
VLSI Design Laboratory, Dept. of Electrical and Computer Engineering, University of Patras, Rio 26 110, Greece, b VLSI Design and Testing Center, Laboratory of Electrical & Electronic Materials Technology, Dept. of Electrical and Computer Engineering, Democritus University of Thrace, Xanthi 67 100, Greece (Received 24 March 1997," In final form 18 January 1998). Of Electrical and Computer Engineering, University of Patras, Rio 26 110, Greece, b VLSI Design and Testing Center, Laboratory of Electrical & Electronic Materials Technology, Dept. A new method for implementing two-level logic circuits, which exhibit minimal power dissipation, is introduced. Switching activity reduction of the logic network nodes is achieved by adding extra input signals to specific gates. Employing the statistic properties of the primary inputs, a new concept for grouping the input variables with similar features is introduced. Appropriate input variables are chosen for reducing the switching activity of a logic circuit. The comparison of the results, produced by the proposed method, and those from ESPRESSO shows that a substantial power reduction can be achieved. Keywords." Low power design, logic circuit, power estimation, switching activity, blocking variable, temporal correlation
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