A New Dynamic Logic Circuit Design with Low Leakage Power

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Dynamic logic circuits are in high demand for designing low power VLSI circuits since they use fewer transistors and take up less space. The issue develops when the dynamic node is discharged incorrectly, even if the pull-down network is turned off during the evaluation phase. Modifying the stacking effect circuitry results in the design of a new dynamic logic model with low leakage power in comparison to previous models. The LTSpice tool is used to demonstrate the robustness of the proposed model, which uses 45nm PTM technology with varying supply voltages and threshold voltages for the OR logic gate operation.