A Novel Dynamic Logic Circuit with Low Leakage Power and Propagation Delay

Abstract

Dynamic logic circuits are used in highly efficient VLSI devices. Problem arises when the dynamic logic circuit’s performance falls due to its high propagation delay and high leakage power. A novel dynamic logic model with low leakage power and propagation delay in contrast to previous models, is developed by modifying stacking effect circuitry. The LTSpice tool is used to illustrate the robustness of the proposed model utilizing 45nm PTM technology for the OR logic gate functionality.