A new congestion-aware routing algorithm in network-on-chip: 2D and 3D comparison

Abstract

Network on-Chip (NoC) is scalable, flexible, modular communication structure for Multi/Many-core architectures. It allows simpler interconnect models with higher bandwidth compared to bus-based architectures. When a message is exchanged inside an NoC, it passes through several routers. When the communication load is high, contention and congestion may appear in central routers, and lead to an increased latency and power consumption. 3D NoC has been proposed as a solution to improve the performances, especially: throughput, latency, and energy efficiency. In this paper, we first report the results of theoretical and practical comparison between 2D and 3D mesh Network-on-Chip topology. We focus on communication supports, especially routing, in the goal of reducing latency and avoiding congestion. Further, we propose a novel exhaustive routing algorithm to avoid and reduce congestion in 2D and 3D NoC. Also, we discuss the implementation of the proposed algorithm in both topologies and the trade-off between their overheads and their performances. We demonstrate the effectiveness of our algorithm using a wide set of synthetic experiments using NOXIM simulator.