A new block-based SSTA method considering within-die variation

Abstract

This paper presents an analytical method for accurate estimation of delay distributions for circuits under (within-die) process variations. The technique is applied for the circuit delay calculation when considering the effect of channel length variation. In the proposed model, instead of obtaining the exact delay distribution profile, statistically important parameters including mean and variance are computed. The proposed model estimates the mean and variance of the delay distribution of the circuit using the technology parameters. It is shown that the proposed statistical model has extremely small error (less than 10%) compared to those of the Monte-Carlo method. The accuracy of the proposed model increases as the technology shrinks. The proposed model can be applied in the delay estimation of logic circuits considering spatial correlations between process parameters.