Abstract
A monolithic, CMOS, constant-fraction discriminator (CFD) was designed and fabricated in a 1.2-/spl mu/, N-well process. This circuit used an on-chip, distributed R-C delay line to realize the constant-fraction shaping. The delay line was constructed of a 4.8-/spl mu/ wide, 500-/spl mu/ long serpentine layer of polysilicon above a grounded second layer of polysilicon. This line generated about 1.1 ns of delay for a 5-ns risetime signal with a slope degradation of only 15%. The CFD also featured dc feedback for both the arming and zero-crossing discriminators to eliminate timing errors caused by offsets. The entire circuit, including the delay line, required an area of 200 /spl mu//spl times/950 /spl mu/. The timing walk for 5-ns risetime signals over the dynamic range from -20 mV to -2 V was less than /spl plusmn/150 ps. Each channel of the CFD consumed /spl sim/15 mW from a single 5-V supply.
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