Integrated constant-fraction discriminator shaping techniques for the PHENIX lead-scintillator calorimeter

Abstract

The suitability of several on-chip constant-fraction discriminator (CFD) shaping methods for use in the multichannel PHENIX Lead-Scintillator detector has been investigated. Three CFD circuits utilizing a distributed R-C delay-line, a lumped-element R-C delay-line, and the Nowlin shaping method have been realized in a standard 1.2-/spl mu/ n-well CMOS process. A CFD using ideal delay-line shaping was also studied for comparison. Time walk for 5 ns risetime input signals over a dynamic range of -2 V to -20 mV was less than /spl plusmn/175 ps, /spl plusmn/150 ps, /spl plusmn/150, and /spl plusmn/185 ps while worst case rms timing jitter measured 85 ps, 90 ps, 100 ps, and 65 ps, respectively, for the four methods mentioned above. Area requirements for the three candidate methods tested including the fraction circuit were 172 /spl mu//spl times/70 /spl mu/, 160 /spl mu//spl times/65 /spl mu/, and 179 /spl mu//spl times/53 /spl mu/, respectively. The fraction circuit area for the external delay-line circuit was 67 /spl mu//spl times/65 /spl times//spl mu/. Each shaping method studied consumed no power from the dc supply.