Abstract
AbstractThe Fourier Transform is a noteworthy calculation in digital signal processing region. An enhanced signal flow graph is required for FFT processor structures, whose sources of information and outputs are in normal order. In this paper, a memory-based conflict-free FFT processor design by utilizing a modified radix-8 DIF (Decimation-In-Frequency) signal flow graph is proposed. The number of iterations is decreased, and therefore, the execution time is low when compared with memory-based radix-4 FFT. The architecture is implemented on Xilinx Virtex-6 FPGA platform. The proposed FFT processor with radix- 8 has reported lower processing time when compared with radix-4 FFT processor.KeywordsFast Fourier transform (FFT)Memory based architectureDecimation-in-frequency (DIF)Modified signal flow graph
Sign-in/Register to access full text options 
Free) 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
