Abstract

With the emergence of energy-starved systems like wireless sensor nodes, it becomes much more of a necessity for important blocks in such systems like the voltage reference (VR) to work at an ultra-low power consumption. Furthermore, the varying requirements of the functional blocks of a wireless sensor node (WSN) entail varying VR requirements, therefore flexibility in the design of VRs is required. This work proposes a novel replica approach for reducing error in stacked 2-transistor (2T) topology proposed by Seok, allowing integration of low-power, low-error, and scalable VRs in WSNs. The proposed design achieved a 140× improvement in the TC while obtaining a 3× reduction in the power consumption for the 4T variant.

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