Ultra-low-power CMOS voltage references: Analysis and optimization regarding technology node

Abstract

Ultra-low-power (ULP) and ultra-low-voltage (ULV) designs have received more attention due to the fact that self-powered systems are potential candidates for enhancing the supply powering of systems-on-chips (SoC). The scaling down of CMOS nodes creates challenges for designers since circuit topologies are often modified in order to guarantee performance under the effects of the next technology. In this paper, the analysis and optimization of ULP and ULV CMOS voltage references (VRs) is advanced by employing four technologies: 180 nm (bulk), 90 nm (bulk), 65 nm (bulk) and 28 nm (FD-SOI). In addition, a variability-aware computer-aided tool (CAD) for the design of ULP and ULV CMOS VRs under the effects of deep-nanometer nodes is described in this paper. Post-layout simulation results show that the CAD tool is capable of designing VRs with excellent Figure-of-Merit (FoM) performance, and the final remarks provide guidance in selecting the best VR topology depending on CMOS technology.