Abstract
The focus of this paper is towards developing an application specific design methodology for low power solutions in recursive coding system in which filtration process is performed by using MAC approach. For the realization of this MAC operation a recursive multiplication and addition operation is carried out. Theconventional recursion results in multiple accumulation operation in successive clocks of duration amounting to that of an addition-time, so that the accumulation of �� successive input words are performed in ��clock cycles. For large values of ��, a computational latency of ��addition-time over head and high power consumption and accumulation process to obtain an accumulated output could be too high to meet the timing requirement in real-time application. so in order to over this problem in this paper a new scalable Repetitive multiply accumulates (MACs) is proposed.From the simulation results the proposed MAC has less delay complexity and low power consumption when compared to the conventional approaches. Keyword: Recursive coding, VLSI, Application specific integrated circuits, digital signal processing chips , digital arithmetic.
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