Abstract
Multiply-accumulator (MAC) is the central unit used in digital signal processors (DSP) that are now widely found in many consumer electronic devices. With current emphasis on minimizing operating power and yet maximizing computation performance for DSPs, efficient MAC architecture with low power consumption and high computation performance is hence desired. This paper proposes a low power pipelined MAC architecture that incorporates a 16×16 multiplier using Baugh-Wooley algorithm with high performance multiplier tree, together with clock gating the idle pipeline stages to reduce the power consumption. Our simulations show that the power consumption of the proposed architecture is 30% to 80% less than the other contemporary MAC architectures, without compromising its computation performance.
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