Low Power Datapath Architecture for Multiply - Accumulate (MAC) Unit

Abstract

This paper presents a high pace and low power datapath architecture for Multiply - Accumulate (MAC) unit using Baugh - Wooley multiplier and with the 4:2 Compressor. Generally, MAC contains Partial- Product generation terms (PP unit) and a reduction tree in first stage. In the following stage there exists an accumulation stage of an adder with the sign extension. Operand sizes of 8, 16 and 32 bits are used over a MAC architecture that performs a multiplication and an accumulation operation. A lower operating frequency for the proposed architecture can be used to down size the gates in the available time slack, resulting in a reduction in lower power, delay, and area. We proposes a new architecture of MAC with compressor and it efficiently performs either multiply-accumulate or multiply operations for N bit operands. The new proposed architecture was realized with respect to the ISE Xilinx PlanAhead tool 14.7 and Cadence RTL compiler by giving the comparison between Ripple carry adder, Carry save adder and Brent-Kung adder.