A Methodology for Testing Arbitrary Bilateral Bit-Level Systolic Arrays

S Bandyopadhyay,A Sengupta,B B Bhattacharya

doi:10.1155/1996/84045

Abstract

In this paper, we discuss the controllability and observability issues in bilateral bit-level systolic arrays. We have introduced a new concept—‘Sj-controllability in M steps’, which is somewhat analogous to the concept of C-testability and refers to the fact that all the cells in the array can be set to the state Sj in at most M steps after initialization. Systolic arrays where the value of M is independent of the length, of the array are characterized. Our testing procedure is based on partitioning the array into several identical subarrays which allows us to apply a repetitive pattern of tests and propagate test outcome to the observable extremities so that every cell in the array is tested by a minimum sequence of tests. Based on this concept,we have developed a set of sufficient conditions for an arbitrary bilateral bit-level systolic array to be testable for single faults.

Highlights

With recent advances in parallel algorithms and their cost effective implementation with VLSI architecture, systolic arrays [1] are being widely used in many areas, e.g., matrix multiplication, graph algorithms, signal and image processing, pattern matching to name a few
C-testability refers to the existence of a constant number of test vectors independent of the length of the array, whereas pI-testability means that the array is partitionable into subarrays having identical test outputs
We explore many interesting features of controllability and observability and present a new set of sufficient conditions for controllability and observability in an arbitrary bilateral bit-level systolic array

Summary

Introduction

With recent advances in parallel algorithms and their cost effective implementation with VLSI architecture, systolic arrays [1] are being widely used in many areas, e.g., matrix multiplication, graph algorithms, signal and image processing, pattern matching to name a few. The well known concepts of C-testability [3]and pItestability 15] originally evolved to provide efficient test scheme for iterative logic arrays (ILA) [13], can be adopted for some systolic arrays because of their repetitive structure. Methods for testing unilateral systolic arrays can be found in [5], [16] and for bilateral arrays in [2,11]. Necessary and sufficient conditions for C-testability and design for testability for both unilateral and bilateral systolic arrays appeared in [14]. A set of sufficiency conditions for testing bilateral arrays of combinational cells have been described in [9], [17]

Objectives

Methods

Conclusion