A Methodology for Quantitatively Introducing ‘Atomistic’ Fluctuations into Compact Device Models for Circuit Analysis

Abstract

As device dimensions enter the decanano regime, ‘atomistic’ fluctuations will play an important role in device mismatch, and become one of the critical issues for high quality analogue and mixed signal IC design. In this paper, we present a two-stage extraction strategy to introduce ‘atomistic’ fluctuation effects into the industry standard compact model BSIM3v3, and integrate their effects into present circuit analysis and electronic design automation (EDA) tools. The methodology is illustrated by statistical parameter extraction for a typical 35 nm gate length nMOSFET, and performance of statistical simulations for a simple cascode current mirror circuit.