Abstract
A component fault isolation procedure is proposed for the robust fault diagnosis of analog circuits. The method exploits the verification fault diagnosis scheme, designed for linear analog circuits, and extended to nonlinear ones. The procedure is divided into two stages. The first stage is based on nonlinear analysis of circuit under test and verification is performed with circuit model linearized in the neighbourhood of the operating point, and the second stage is based on nonlinear analysis of circuit with only some nonlinear devices modeled by piecewise-linear (PWL) function. This economical approach keeps the computation time within the acceptable limits in comparison with entire PWL model approach and diagnosis is accomplished at low measurement cost.
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