Abstract
A component fault isolation procedure is proposed for the robust fault diagnosis of analog circuits. The method exploits the verification fault diagnosis scheme, designed for linear analog circuits, and extended to nonlinear ones. The procedure is divided into two stages. The first stage is based on nonlinear analysis of circuit under test and verification is performed with circuit model linearized in the neighbourhood of the operating point, and the second stage is based on nonlinear analysis of circuit with only some nonlinear devices modeled by piecewise-linear (PWL) function. This economical approach keeps the computation time within the acceptable limits in comparison with entire PWL model approach and diagnosis is accomplished at low measurement cost.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
