A Low-Power Three-Tap DFE with Switched Resistor Slicer and CTLE in 0.18μm CMOS Technology

Abstract

In this paper, a switched resistor slicer is proposed to reduce the power consumption of a decision feedback equalizer (DFE). In the proposed structure, summer circuit that consumes most of the power in a DFE has been eliminated and proper resistors are added as the load of a slicer based on a flip-flop output bit stream. Incorporating the proposed DFE circuit with continuous time linear equalizer (CTLE) at the serial link receiver over a 1[Formula: see text]m NELCO (the NELCO[Formula: see text] N4000-13 series is an enhanced epoxy resin system engineered to provide both outstanding thermal and high signal speed/low signal loss properties) channel can compensate 24[Formula: see text]dB loss at the Nyquist frequency of 2[Formula: see text]GHz. CTLE is adjusted to compensate 6[Formula: see text]dB of channel loss which remains after utilizing a DFE with three taps. The proposed structure has been designed in 0.18[Formula: see text][Formula: see text]m CMOS technology while consuming 13.5[Formula: see text]mW from 1.8[Formula: see text]V supply at 4[Formula: see text]Gb/s with a bit error rate less than 10[Formula: see text]. The proposed equalizer power consumption is reduced by 43% compared to the conventional circuit.