A 37.8dB Channel Loss 0.6μs Lock Time CDR with Flash Frequency Acquisition in 5nm FinFET

Abstract

High-speed SerDes is accompanied by high channel loss. Channel loss is usually compensated by transmitter feed-forward equalization (FFE), receiver continuous time linear equalization (CTLE), and receiver decision-feedback equalization (DFE). However, the FFE, CTLE, and DFE can only adjust compensation strength after the CDR is locked. Without well-compensated channel loss, it is difficult for a CDR to lock to input data with significant frequency offset. Several frequency detection techniques are presented in [1–3], but the effect of channel loss on the behavior of CDR locking is less addressed. Achieving fast lock time under high channel loss is a challenge for CDR circuit design. In [3], a stochastic PFD weights three consecutive patterns, data-edge-data, to obtain frequency information. However, the calculated pattern weighting may vary with different channel losses. Moreover, it can only obtain the sign of the frequency offset as a conventional approach. In this work, a CDR with a flash frequency acquisition (FFA) technique is proposed. The proposed CDR adopts open-loop frequency acquisition to avoid noise accumulation in a closed-loop operation. The sampled data from a bang-bang phase detector forms a time series. The FFA uses an autocorrelation network with weighting information and autocorrelation function, borrowing concepts from a RNN, to acquire frequency offset. By using FFA, this CDR acquires the magnitude of frequency offset under 37.8dB channel loss. Thanks to the magnitude of the frequency offset, the proposed CDR achieves lock time independent of frequency offset.