A 16Gbps 3rd Order CTLE Design for Serial Links with High Channel Loss in 16nm FinFET

Abstract

As the size of the transistor is shrinking to improve the performance of the chip, the on-chip communication speed has outperformed the off-chip communication speed. The performance of the system that consists of multiple IC's is limited by off-chip communication speed. The chip-to-chip communication speed is typically at Giga-Hertz range for high-speed transceiver system. The digital data transmitted at these higher speeds will not be able to retrieve at the receiver side due to inter symbol interference (ISI) caused by lossy channel. The bandwidth of the channel is not improving at the same pace as compared to data rates. To compensate the high frequency losses introduced by the channel, Continuous Time Linear Equalizer (CTLE) is used at receiver front end. The CTLE is normally implemented in first order. The higher order CTLE offers the advantage of incremental gain peaking when dealing with higher data rates and long channels which has high losses. In this paper, third order CTLE equalizer is designed for receiver front end for 16-Gbps data rate SERDES to achieve minimum eye height of 30mV and minimum eye width of 0.2 UI (i.e. 12.5 ps) for the channel loss of 30dB @ 8GHz in 16 nm FinFET technology and compared the simulation results with first order and second order CTLE equalizers.