A Low-power and High-performance Radix-4 Multiplier Design Using a Modified Pass-transistor Logic Technique

Abstract

This paper describes a 1-bit adder designed using the modified complementary pass transistor logic technique. The proposed adder was implemented in an 8 × 8 bit high radix multiplier circuit. This paper describes the proposed adder technique for obtaining high speed, lower area, less power dissipation and lower propagation delay. The multiplier circuits were schematized using the DSCH2 schematic design tool, and their layouts were generated with the Microwind 2 VLSI layout CAD tool. The parameter analyses were performed with a BSIM4 analyzer. Two unsigned multipliers were designed using the proposed modified complementary pass-transistor logic (CPL) adder cell, namely a Carry Save Array multiplier (CSA multiplier) and a Baugh-Wooley multiplier, for comparison with our proposed adder cell-based high radix multiplier. The proposed adder cell-based CSA multiplier and Baugh-Wooley multiplier, as well as other existing multipliers, were compared with the high radix multiplier circuit in terms of power dissipation, propagation delay, latency, throughput, Energy Per Instruction and area. Our proposed 1-bit adder and adder-based high radix multipliers demonstrated better performance than other published results.