A Low-Power and Area-Efficient 14-bit SAR ADC with Hybrid CDAC for Array Sensors

Abstract

This paper proposes a low-power and area efficient 14-bit Successive Approximation Register (SAR) analog-to-digital converter (ADC) for array sensors. A hybrid capacitor digital-to-analog converter (CDAC), which consist of a 10-bit split CDAC and a 5-bit serial CDAC, is utilized to increase the area efficiency. The total required number of unit capacitors are only 52. A foreground digital calibration is employed to compensate the linearity error caused by the capacitor mismatch and bridge parasitic capacitor. The HSPICE post-layout simulation results show that the peak DNL and INL of the proposed ADC are enhanced from 1.27/-1 LSB and 17.29/-16.24 LSB to 0.74/-0.49 LSB and 1.27/-0.54 LSB, respectively. And ENOB is improved from 9.82bit to 13.65 bit at 48.14-KHz input after calibration. With a power consumption of 59 µW, the FOM is 45.42 fJ/step. The CDAC occupies an active area of 15 × 800 µm2 and the area efficiency ADC core is only 0.934 µm2/code.