A Low-Power Adiabatic Multiplier Based on Modified Booth Algorithm

Abstract

This paper presents an adiabatic array multiplier based on modified Booth algorithm. It is composed of Booth encoders, a multiplier array containing partial product generators and 1-bit (half and full) adders, and a final carry-look ahead adder. All circuits are realized with DTGAL (dual transmission gate adiabatic logic) circuits using 0.18 mum TSMC process. The energy loss of the proposed adiabatic Booth encoders, partial product generators and full adders is compared with its corresponding CMOS implementations. The simulation results show that the proposed adiabatic Booth encoder attains energy savings of 92.5% at 50 MHz and 78.3% at 300 MHz, compared with its CMOS counterpart. The adiabatic partial product generator and 1-bit full adder attain energy savings of 88.5% and 75.6% as compared to the conventional CMOS implementations at 200 MHz, respectively.