Abstract
This paper presents an adiabatic multiplier for low-power DSP. A dual transmission gate adiabatic logic (DTGAL) suitable for pipelined structures is described. It can recover the charge of load nodes by using feedback control from next-stage buffer outputs to realize power-efficient design. An 8/spl times/8-bit adiabatic multiplier based on our DTGAL is designed. The power consumption of the proposed multiplier is significantly reduced because the energy transferred to the load capacitance is mostly recovered. Functional and energy simulations are performed for the multiplier using the net-list extracted from its layout. HSPICE simulations indicate energy savings of 65% to 85% as compared to the conventional CMOS implementation for clock rates ranging from 25 to 200 MHz.
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