Abstract
Power-efficient multipliers are essential for low-power signal processing hardware and embedded digital system since they have high switching activity and contain large node capacitances, resulting in large power dissipation. This paper presents an adiabatic Booth array multiplier based on PAL-2N circuits. It is composed of Booth encoders, a multiplier array containing partial product generators and 1-bit (half and full) adders, and a final carry-lookahead adder. Full-custom layouts are drawn. The energy and functional simulations have been performed using the net-list extracted from their layouts. The simulation results show that the adiabatic Booth array multiplier attains large energy savings, compared with its counterpart without the booth encoder.
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