A low power time-interleaved 10-bit 250-MSPS charge domain pipelined ADC for IF sampling

Abstract

A 10-bit 250-MSPS two-channel time-interleaved charge-domain (CD) pipelined analog-to-digital converter (ADC) is presented. MOS bucket-brigade device (BBD) based CD pipelined architecture is used to achieve low power consumption. An all digital low power DLL is used to alleviate the timing mismatches and to reduce the aperture jitter. A new bootstrapped MOS switch is designed in the sample and hold circuit to enhance the IF sampling capability. The ADC achieves a spurious free dynamic range (SFDR) of 67.1 dB, signal-to-noise ratio (SNDR) of 55.1 dB for a 10.1 MHz input, and SFDR of 61.6 dB, SNDR of 52.6 dB for a 355 MHz input at full sampling rate. Differential nonlinearity (DNL) is +0.5/−0.4 LSB and integral nonlinearity (INL) is +0.8/−0.75 LSB. Fabricated in a 0.18-μm 1P6M CMOS process, the prototype 10-bit pipelined ADC occupies 1.8 × 1.3 mm2 of active die area, and consumes only 68 mW at 1.8 V supply.