A low power high area-efficiency NMOS LDO with fast adaptive bias

Abstract

A low power consumption and fast transient response NMOS low dropout voltage regulator (LDO) with fast adaptive bias is proposed in this work. As a buffer between error amplifier and pass device in LDO, the symmetric flipped voltage follower could ensure stability and speed up the load transient response. In order to obtain better transient response performance and lower power consumption at quiescent state, an adaptive bias is used to generate adaptive current in different proportions, from load current to error amplifier and symmetric flipped voltage follower. The proposed LDO is designed in a 180 nm CMOS process with only 0.005 mm2 active area. Under the condition of typical process corner, the DC loop gain is at least 42.81 dB, and the phase margin ranges between 51.6° and 113.6°. Despite only 2.91μA quiescent current, the LDO with sub-microsecond settling time as low as 1ns at the edge of the load current change has little overshoot/undershoot.