Abstract
A SOI (Silicon-On-Insulator) LD (Lateral Double-diffused) MOS with an EIR (Elevated Internal Ring) is proposed to reduce the on resistance without decreasing the breakdown voltage by elevating the internal field ring to the surface of the drift layer. The EIR is formed by a self-aligned process without an additional mask. The characteristics of the EIR LDMOS are verified by the two-dimensional process simulator, TSUPREM4 and the device simulator, MEDICI. In case of 200 V LDMOS, the on resistance of the EIR device is decreased by 43% and 10.5%, respectively when compared with those of the conventional devices with an internal ring and a step gate oxide.
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