Numerical and Experimental Investigation on a Novel High-Voltage ( $>$ 600-V) SOI LDMOS in a Self-Isolation HVIC

Abstract

In order to achieve a high breakdown voltage (BV) and to realize self-isolation in high-voltage ICs (HVICs), a novel high-voltage n-channel lateral double-diffused MOS (LDMOS) with a buried n-island layer (BNIL) placed at the interface between a p-type silicon-on-insulator (SOI) layer and a buried-oxide (BOX) layer (BNIL SOI) is proposed. Its breakdown mechanism is investigated theoretically and experimentally. In a high-voltage blocking state, the ionized donors in the depleted n-islands make the electric field in the n-islands monotonously increase rather than decrease, as exhibited in the p-SOI region. This leads to an increase in the SOI layer bottom-interface field strength from 10 V/μm in the conventional p-SOI to 27 V/μm in the BNIL SOI, and as result, the electric field strength in the BOX, i.e., EI, increases from 30 to 82 V/μm. The holes collected in the space between the depleted n-islands help maintain the high EI. Consequently, the BV is enhanced. The p-SOI layer, along with the implanted n-drift region and discontinuous buried n-islands, is demonstrated to have enhanced self-isolation, which removes the need for deep dielectric isolation trenches in power ICs. The dependence of breakdown characteristics and isolation performance on the structure parameters has been analyzed. A test self-isolation SOI HVIC with a 660-V BNIL LDMOS has been fabricated in a 20-μm SOI layer over a 4-μm BOX layer, which has verified the feasibility and validity of the new concept.