A low loss double‐pole double‐throw switch in 65 nm CMOS for wigig applications

Abstract

ABSTRACTThis article presents a 60 GHz low insertion loss double‐pole double‐throw (DPDT) switch implemented in 65 nm standard CMOS process. To achieve the low insertion loss, various techniques are used such as the double‐well body‐floating, gate‐floating, high‐performance thin‐film microstrip line, resonating the capacitance of the off‐state transistor, and the transmission line based matching network. To achieve both high performance and small area, EM simulations are intensely performed to model passive components. The DPDT switch achieves insertion loss of less than 2.7 dB, and return loss of better than 10 dB over the 52–66 GHz band. The measured IIP3 is 18 dBm (simulated IP1dB is 11.4 dBm). The fabricated DPDT switch has an effective area of 0.073 mm2. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:2864–2867, 2014