Improved IIP3 double‐pole double‐throw switch with body and gate floated multi‐stack resonator in 65 nm CMOS for WiGig applications

Abstract

A 60 GHz improved IIP3 double-pole double-throw (DPDT) switch using body and gate floated multi-stack resonator implemented in 65 nm CMOS technology is presented. To improve the IIP3, multi-stack and resistive body-floating techniques are used. To decrease the insertion loss, the resistive body-floating, gate-floating and resonant inductor techniques are used. This DPDT switch is designed to have effective size using body and gate floated multi-stack resonator. IIP3 is better than 27.5 dBm in 58.8–65.3 GHz. Insertion loss is <3.3 dB in 57–66 GHz. Return loss is better than 10 dB in 49–68 GHz.