A low kickback fully differential dynamic comparator for pipeline analog‐to‐digital converters

Jose‐Angel Diaz‐Madrid,Johann Hauer,Gines Domenech‐Asensi,Loreto Mateu

doi:10.1002/eng2.12055

Abstract

This study presents a fully differential dynamic comparator with low kickback noise, an effect caused by voltage variations in the regeneration nodes of these types of circuit. Given their low power dissipation, dynamic comparators are key circuits in analog‐to‐digital converters (ADCs), especially in pipelined ADCs. The proposed comparator has been simulated and compared with three other comparator topologies. The value of the kickback noise generated by the proposed circuit is lower than that generated by other conventional dynamic comparators over a wide input range, while simultaneously showing a low offset voltage error. The dynamic comparator has been implemented in a low‐resolution ADC with a resolution of 2.5 effective bits, which has been prototyped in a 0.35‐μm CMOS AMS C35B4 process. Its size is 34 μm × 38 μm.

Highlights

The rapid development of portable electronic devices using wireless data and video protocols has prompted the use of increasingly low power mixed signal circuits, analog-to-digital converters
Kick-back effect or kick-back noise is caused by voltage variations in the regeneration nodes of the dynamic comparator 3 and the coupling of the digital input and output of the circuit to its analog input voltage
The value of the kick-back noise generated by the proposed circuit is lower than that generated by other conventional dynamic comparators over a wide input range, whilst, simultaneously, the offset voltage error is remained in the working range and the power consumption is extremely low

Summary

INTRODUCTION

The rapid development of portable electronic devices using wireless data and video protocols has prompted the use of increasingly low power mixed signal circuits, analog-to-digital converters Given these specifications, pipelined ADCs are popular architectures for high-speed data conversion (10-100 MS/s) at medium to high resolution (8-14 bits) 1. Contrary to the noise power, the offset voltage , than can be allowed in the comparators depends exclusively on the topology of the stage and the reference voltage The value of the kick-back noise generated by the proposed circuit is lower than that generated by other conventional dynamic comparators over a wide input range, whilst, simultaneously, the offset voltage error is remained in the working range and the power consumption is extremely low.

CIRCUIT IMPLEMENTATION

SIMULATIONS

EXPERIMENTAL RESULTS

CONCLUSIONS