A low jitter delay-locked loop with a realignment duty cycle corrector

Abstract

In this paper, a new delay-locked loop (DLL) architecture is proposed to effectively improve the DLL jitter performance. A novel duty cycle corrector (RDCC) is proposed for the DLL. The RDCC circuit can make the output waveform of the DLL maintain a 50% duty cycle in a lock mode. The RDCC circuit has advantages of low power consumption, small chip area and high operating frequency. The proposed DLL adopts the clean ref-clock signal and the locked signal to do the realignment operation, which improves the jitter performance. The DLL is designed using the TSMC 0.35mum 2P4M CMOS technology. HSPICE simulation results show that the proposed DLL jitter is effectively reduced 61% at 250MHz with a 3.3V supply