A fast locking and low jitter delay-locked loop using DHDL

Abstract

A fast-locking and low-jitter delay-locked loop (DLL) using the digital-controlled half-replica delay line (DHDL) is presented. The DHDL can provide stable bias voltage for the charge-pump circuit to achieve low-jitter performances; meanwhile, the property of bandwidth tracking can still be preserved. It can also provide a larger pumping current to reduce the lock time in the initialization state and provide a smaller current to improve jitter performance in the locked state. For comparisons, both the proposed DLL and the self-biased DLL have been fabricated in a 0.35-/spl mu/m one-poly four-metal CMOS process. From the measurement results, the proposed DLL has a shorter lock time and a better jitter performance than the self-biased DLL. The root-mean-squared jitter and peak-to-peak jitter are less than 4.2 and 30 ps, respectively, occurring at 75 MHz, over an operating frequency range of 50-150 MHz.