A Low-Cost CMOS Smart Temperature Sensor Using a Thermal-Sensing and Pulse-Shrinking Delay Line

Abstract

This paper presents an economical time-domain CMOS smart temperature sensor with only one delay line. With the use of a path selection circuit, the delay line was used to first sense the temperature, to generate a pulse with a width proportional to absolute temperature (PTAT). The original delay line was then reused to measure the PTAT pulse. Final digital code conversion was fulfilled using a simple counter. Compared with former work with two delay lines, the proposed work with the novel structure can reduce one delay line to lower the circuit area. The proposed circuit was fabricated in a TSMC CMOS 0.35- μm 2P4M digital process, and had an extremely small chip area of 0.025 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , which is currently the best size among smart temperature sensors that has ever been reported when considering the CMOS process. The achieved measurement errors for eight chips are within -0.8 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C-1.0 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C after two-point calibration over a 0 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C-100 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C temperature range. The effective resolution is measured to be 0.2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C, and the power consumption is 1.5 μW at a sampling rate of 10 samples per second.