An accurate CMOS delay-line-based smart temperature sensor for low-power low-cost systems

Abstract

To realize the on-chip temperature monitoring of VLSI chips, an accurate but low-cost CMOS smart temperature sensor based on delay lines is proposed. Without any bipolar transistor, a temperature-to-time generator composed of two delay lines is used to generate a time interval inversely proportional to the measured temperature first. Then, a time-to-digital converter (TDC) rather than a voltage or current analogue-to-digital converter (ADC) is utilized to convert the time interval into the corresponding digital code. The same thermal compensation scheme used in the temperature-to-time generator is also adopted in the TDC to enhance the linearity and resolution of the proposed circuit. Furthermore, every thermal compensation circuit is shared by two adjacent cells to reduce both chip size and power consumption. The test chips were fabricated in a TSMC CMOS 0.35 µm 2P4M digital process and have an extremely small area of 0.09 mm2, which is less than one-twentieth of most predecessors'. The achieved resolution and measurement error are reduced from 0.16 °C, −0.9–0.7 °C of the former version to 0.09 °C, ±0.6 °C after two-point calibration, but without any curvature correction or dynamic offset cancellation. The power consumption is about 1.5 µW at a sampling rate of 5 samples/s and a measurement rate as high as 10 kHz is feasible.