A Linting tool without a compiler in it

Abstract

Register Transfer Level (RTL) linting is an important step in the front-end design methodology for every chip design process [5]. This technique helps to accelerate the discovery and diagnosis of design flaws early, reducing the overall development cycle for complex SoC designs [11] [12]. No one else has tried to develop an RTL level linting tool before using iVerilog extension framework. The novelty of this approach is that the verilog/vhdl compiler remains outside the linting tool. So the linting tool remains light and does not carry the heavy compiler with it. Icarus verilog, popularly known as iVerilog, is an established open source mixed language compiler-simulator-synthesis framework [1]. It is covered by GPL. It has wonderful APIs which can be used to create extension programs of iVerilog. We have used this extension capability to develop our new linting tool. This tool is supposed to work with any version of iVerilog. We have tested our tool with iverilog version 10, 11 and 12 extensively and found to be working fine with these versions. Electronic Design Automation (EDA) tools are absolutely must in the field of VLSI design. There are many companies which develop EDA tool but they are extremely costly [8]. Open-source EDA tools plays a vital role in this are. In this paper we have described such a tool, iLint, which we have developed and named it - iLint.