A Layout-Based Soft Error Rate Estimation and Mitigation in the Presence of Multiple Transient Faults in Combinational Logic

Abstract

Cosmic radiation resulting in transient faults to the combinational logic of Integrated Circuits (ICs), constitutes a major reliability concern for space applications. In addition, continuous technology shrinking allows for the presence of Single-Event-Multiple-Transients (SEMTs), and renders modern chips more susceptible to soft errors. The study and evaluation of the impact of such errors on ICs functionality, as well as the pursuit of techniques to mitigate Soft Error Rate (SER), tend to become an essential part of the design process. This paper presents a Monte-Carlo-based SER estimation method, taking into account all masking mechanisms, which determines the vulnerable areas of a circuit based on layout information. Two layout-aware approaches are examined, the All-to-All and TMR-based, resulting in sufficient SER mitigation. The former, implies spacing among all components, while the latter converts the most sensitive components to a TMR structure, guaranteeing spacing between TMR triplet. The TMR-based approach leads to better SER mitigation compared to All-to-All, and produces better area and performance results.